Escalating demands for high density and performance associated with ultra large scale integration require semiconductor devices with design features of 0.25 microns and under, e.g. 0.18 microns, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional semiconductor technology for isolating active regions.
Conventional semiconductor devices comprise a substrate having various electrically isolated regions, called active regions, in which individual circuit components are formed. The active region typically includes source/drain regions of a transistor formed in the semiconductor substrate or epitaxial layer, spaced apart by a channel region. A gate electrode for switching the transistor is formed on the channel with a gate oxide layer therebetween. The quality and thickness of the gate oxide are crucial for the performance and reliability of the finished device.
The electrical isolation of these active regions is typically accomplished by defining field regions bounding the active regions, defined by a source/drain mask applied to a barrier nitride layer deposited over the semiconductor substrate, typically doped monocrystalline silicon or an epitaxial layer formed thereon. Thermal oxidation of semiconductor substrate in the exposed field regions is typically employed to form the field oxide isolation structure that isolates the active regions.
For example, one type of isolation is known as Local Oxidation Of Silicon (LOCOS), in which the entirety of the field oxide is formed by heating the substrate with the field regions exposed to an oxidizing gas, such as oxygen or water vapor. LOCOS methodology, however, disadvantageously results in the formation of a field oxide region having tapering edges, because the oxidizing species for forming the field oxide diffuses horizontally once it has penetrated the substrate. This tapering end portion resembles and, therefore, is commonly referred to as, a "bird's beak."
LOCOS methodology is thus subject to several inherent problems. For example, while the horizontal extent of the bird's beak can be loosely controlled by the stress induced in the masking layers adjacent to the field, this same stress can cause strain defects in the active areas including point defects, dislocations, stacking faults, as well as catastrophic failures such as delamination, particle generation, etc. Moreover, the aggressive scaling of gate electrode dimension into the deep submicron regime, such as less than about 0.25 microns, requires tighter source/drain region to source/drain region spacing, which is adversely affected by the bird's beak attendant upon LOCOS methodology.
Another type of isolation is known as shallow trench isolation (STI). This form of isolation is typically accomplished by etching a trench in the substrate, conducting a thermal oxidation step to grow an oxide liner on the trench walls to control the silicon-silicon dioxide interface quality, and filling the lined trench with an insulating material, such as silicon dioxide derived from tetraethyl orthosilicate (TEOS). The surface is then planarized, as by chemical-mechanical polishing (CMP), to complete the trench isolation structure. A typical trench isolation structure thus comprises an internal surface with side surfaces extending into the substrate (or epitaxial layer) with edges at the main surface of the substrate and at the bottom of the trench.
Certain semiconductor devices have circuit components operating at different voltages. For example, a FLASH memory device comprises core circuitry that stores the memory bits and peripheral circuitry for decoding row and column addresses. For enhanced operating speed, it is desirable to operate the core circuitry at a fairly low voltage, such as about 1.8 V to about 2 V. The peripheral circuitry, however, is typically operated at a higher voltage, such as 5 V, for reliability concerns. As another example, certain speed-critical components of a microprocessor are typically operated at a lower voltage, but less speed-critical components of the microprocessor are operated at a higher voltage.
The isolation of circuit components is affected by the operating voltage of the circuit components. In particular, a higher operating voltage necessitates a thicker field oxide region to achieve a desired amount of isolation. For example, a field oxide region grown by LOCOS to a depth of about 2000 .ANG. to about 2500 .ANG. the main surface of the substrate can isolate circuitry running at about 1.8 V to about 2 V. However, circuitry operating at about 5 V requires a field oxide region grown by LOCOS to about 4000 .ANG. in depth, which is almost twice as thick. For shallow trench isolation, the required depths for circuit components operating at about 2 V and 5 V are respectively about 2000 .ANG. and about 3500 .ANG..
In general, deep field isolation structures are undesirable. For example, deeper isolation trenches tend to have side walls that are more vertically aligned and induce stress, which is transmitted to the adjacent active regions and degrades the gate oxide grown thereon. As another example, deeper LOCOS field oxide structures tend to exhibit a more extensive bird's beak, limiting the useful area of the adjacent active region.
Due to these disadvantages associated with deep isolation structures, it is generally desirable to avoid manufacturing isolation structures deeper than necessary. However, a common depth for the field oxide isolation structures must be deep enough to isolate the circuit components operating at the highest voltage but deeper than necessary for those circuit components operating at a lower voltage. Thus, semiconductor devices that have circuit components operating at different voltages and, hence, requiring different minimum depths of field oxide for isolation, are typically manufactured with field oxide isolation structures at the different depths sufficient to achieve isolation of active regions.
A conventional approach to manufacturing isolation structures of different depths comprises separately forming each set of isolation structures. For example, in a FLASH memory, the isolation for the core is created first by depositing a thick nitride layer, patterning the thick nitride layer to define the core field oxide regions, as by masking and etching, and then creating the core isolation structures, as by LOCOS or trench etch and fill. The patterned thick nitride layer is then stripped off, and a second thick nitride layer is deposited for the peripheral isolation structures. This second nitride layer is then patterned, as by masking etching, to define the peripheral field oxide regions. Thereupon, the peripheral isolation structures are created to a greater depth than the core isolation structures. It is evident that this conventional approach is complex, costly, and time-consuming, requiring many manufacturing steps, for example, two thick nitride deposition steps or two trench etch steps.